1. Field of the Invention
This invention relates generally to the design and fabrication of integrated circuits. More specifically, it relates to methods and apparatus for reducing leakage currents in integrated circuits, the integrated circuits being at least partially comprised of standard logic cells.
2. Description of the Related Art
In known integrated circuits (ICs), leakage currents have become a significant waste of power. As IC operating voltage has dropped, the threshold voltage (VT) required to turn on the transistors in the IC has also dropped. At this lower VT transistors do not turn on and off in a “hard” manner and increasingly large amounts of current flow through the transistors even when the transistors are nominally off. This current is known as leakage current and currently comprises a significant source of power wastage in ICs.
With ever diminishing transistor size, the effects of these leakage currents have increased. Each new process generation experiences roughly a 5-10× increase in leakage currents through the transistors. At current 0.13 μm to 90 nanometer (nm) transistor size, the problem has become increasingly urgent. At these reduced transistor sizes and decreased VT, leakage currents use an increasing proportion of the total power consumed by the IC. Additionally, the heat generated by the leakage currents is undesirable and the leakage currents themselves may affect the reliability of the IC.
It is currently known that a transistor's leakage current can be reduced by modifying its electrical properties. Two known ways to accomplish this are increasing the transistor's channel length or doping the transistor's channel, increasing its VT. Both methods share the same drawback, which is that a transistor so modified operates more slowly than an unmodified transistor.
One way to mitigate this disadvantage is to use these low leakage, but slow operating transistors strategically at the cell or block level so that the slower transistors impact the performance of the completed IC only minimally. These “strategically placed” transistors would be modified in some way during layout to incorporate either high VT doping or larger channel lengths, or both to reduce their leakage currents.
In some standard logic cell libraries, two sets of standard logic cells are created, the first operating at a higher speed with greater leakage currents and the second set operating at a slower speed but with reduced leakage currents, the reduced leakage currents effected by doping the transistors' channels in a known manner. A designer can then choose various combinations of cells from both sets to obtain the required performance and minimum leakage current in the final circuit design. This approach reduces the total chip level leakage current whenever a reduced leakage cell is used in the place of high performance, high leakage cell. However, many transistors in a high performance cell can be replaced with lower leakage transistors without reducing the performance of the overall design, since multiple signal paths exist in most logic cells, and normally only one of these paths determines the overall chip level performance. The present solution of using combinations of high performance and low leakage cells leaves a number of high leakage transistors as part of the high performance cells that could safely be replaced by low leakage transistors.
A method to allow chip level designer to create a design that achieves target timing performance and also further reduces leakage current by maximizing the number of low leakage transistors used would therefore be desirable.